Solving Challenges for Next-Generation Advanced Packaging Lithography Processes

Blogs | 2022년 5월 03일

In the world of microelectronics manufacturing, the process of connecting integrated circuit (IC) die to the printed circuit board (PCB) is called semiconductor packaging. Traditionally, the interconnect method used between ICs and their packaging has been wire bonding. For more advanced technology nodes, however, other methods of interconnect that comprise advanced packaging technologies have been used. These included techniques such as Cu bump, fan-in wafer-level packaging (FIWLP), fan-out wafer-level packaging (FOWLP), 2.5D interposers and 3D stacking using hybrid bonding. All of these approaches are designed to accommodate increasingly higher interconnect density.

Until recently, wire bonding dominated the packaging market. But as semiconductor nodes continue to shrink, wire bonding doesn’t provide high enough interconnect density, which translates to slower data rate speeds. As a result, advanced packaging technologies are poised to take some significant market share from traditional approaches to packaging. Analysts predict the advanced packaging market will grow at a compound annual growth rate (CAGR) of 8% over the next five years.

그림 1: 2021 Yole Advanced Packaging report

Applications like artificial intelligence (AI), 5G networks and high-performance computing (HPC) are producing an avalanche of data that is expected to grow at an exponential rate. In the next five years, interconnect density will continue to increase, driving finer feature requirements across advanced packaging platforms including FIWLP, FOWLP, substrates, 2.5D, 3D and system integration. Figure 2 breaks down the I/O density, line/space and bump pitch requirements, as well as the number of redistribution layers based on application.

These requirements are impacting the packaging techniques used to create advanced packaging structures. In particular, lithography and the associated wet processes including etch and photoresist strip are experiencing challenges across the process landscape from bumps, pillars and RDLs, to through silicon vias (TSVs), interposers and hybrid bonding.

 

그림 2: Increasing interconnect density requirements over the next five years will drive the need for smaller line/space requirements.

 

Advanced Packaging Lithography Challenges
As feature sizes shrink to match the incoming IC nodes </=7nm, advanced packaging lithography processes are moving closer to front-end steps, into the submicron realm. Moreover, feature sizes vary from process to process. For example, leading-edge features for under bump metallization (UBM) and Cu pillars range from 2-10µm all the way up to the 20-30µm range. This requires an advanced packaging lithography system that can handle a wide range of resist thicknesses varying from 1-2µm up to 60-80µm, depending on the process flow.  Additionally, more RDL layers mean more films on ultra-thin wafers, resulting in wafer warpage. These wafers can be difficult to handle. Lastly, increased I/O density requires shrinking resolution.

With the introduction of fan-out panel-level packaging (FOPLP) and chiplet integration, package sizes are getting larger. Reticle sizes aren’t always large enough to capture the entire image, so the images must be captured separately and stitched together. Today’s FOPLP and chiplet packages sizes range from 15x15mm to 20x20mm. As it currently stands, there are no standards for panel sizes or for chiplet models. So, flexibility is the key.

 

Advanced Packaging Lithography Solutions

Handling the breadth and depth of advanced packaging lithography challenges requires a system that is flexible enough to handle both i-line and broadband processing. In this way, it can cost-effectively support resolutions ranging from the leading-edge at 2µm/2µm line/space (l/s) all the way to the trailing edge, measured in tens of microns l/s.

Leading edge processes typically operate in I-line mode for improved resolution. However, the resist material adds cost to the process, so trailing-edge processes that are more cost-sensitive are better run using GHI mode.

This calls for a light source that is broadband compatible to take illumination band from 350nm all the way to 430-440nm. so that it captures more energy. The result is higher throughput and better process control for both thick and thin resists. Additionally, to meet varied devices and requirements, tool-to-tool matching is critical to achieving high yields.

 

Conclusion
At Veeco, we continue to lead the market in advanced packaging lithography because of flexible solutions built right into our tools. Our systems feature 1x optics and low numerical aperture to provide a large depth of focus, which expands the process window. We provide both 68mm X 26mm and 61mm X 33mm field size options to address a variety of package sizes without sacrificing productivity. Broadband and i-line mode support a complex product mix, and broadband illumination supports best cost-of-ownership and flexibility. Additionally, we offer a suite of wet processing tools specifically designed to handle the challenges of next-generation advanced packaging process flows. Click here to learn more about Veeco’s advanced packaging offering.

 

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